1. Field of the Invention
The present invention relates to current mode logic circuits, and more particularly, to a method and circuit for resetting current mode logic circuit elements that have a memory and/or initial state.
2. Related Art
Current mode logic (CML) is widely used to build high speed logic blocks, such as frequency dividers in PLLs and high speed serial link transceiver circuits. CML logic can operate two to three times faster than CMOS logic. For frequency dividers and counters, there is often a need to implement a reset to enable initialization of a defined state. In CMOS logic, this is done by using the resetable flip flops, which are typically implemented by having pull-up or pull-down transistors enabled in the reset state. Since CMOS logic is a complementary-type logic, where one path is turned ON and the other OFF, it is straightforward to use pull-up, pull-down and pass switch transistors to implement the reset. In CML, latches are realized using biased differential transistor pairs and crossover switches, and, unlike CMOS latches, speed and bias requirements do not easily allow a reset to be done by using pass transistors switches with pull-ups and pull-downs. A reset method commonly used in CML is described below.
In conventional art, which is illustrated by a divide-by-N circuit of FIGS. 1-7, a multiplexer 101 provides the initial state of the divide-by-N, and the reset mechanism is done sequentially from the input (vip, vin) to the output (vop, von). This is illustrated in FIGS. 1-7. The conventional CML divide-by-N circuit with an asynchronous reset shown in FIG. 1 consists of three blocks:
N CML flip flops 103A-103N are connected in series. Each CML flip flop 103 (illustrated in detail in FIG. 2) has two series-connected latches 201A, 201B and each latch 201A, 201B (illustrated in detail in FIG. 3) has NMOS differential transistor pair M301, M302, NMOS cross-coupled transistor pair M303, M304, NMOS transistor switches M305, M306, NMOS current source M307 and resistors R301, R302.
CML combination logic 102 (illustrated in detail in FIG. 4), includes NAND, NOR and MUX gates, and sets a duty cycle of divide-by-N circuit output.
CML multiplexer 101 (see FIG. 5) has NMOS differential transistor pairs M501-M502, M503-M504, NMOS transistor switches M505, M506, NMOS current source M507 and resistors R501, R502. Multiplexer 101 with one input connected to (VSS, VDD) provides the initial state and isolates the unknown input signal disturbing the reset process when reset is positive.
FIG. 2 shows a structure of CML flip flop 103. As shown in FIG. 2, CML flip flop 103 includes two CML latches 201A, 201B connected in series. CML latch 201A has inputs (vip, vin), and outputs (vop, von) which are inputted into corresponding inputs (vip, vin) of the second CML latch 201B. Both latches 201A, 201B have common clock inputs (clk, clkn).
FIG. 3 shows a structure of a CML latch 201 of FIG. 2. As shown in FIG. 3, CML latch 201 has a differential transistor pair M301, M302, whose gates are driven by (vip, vin) respectively. CML latch 201 also has an NMOS cross coupled transistor pair M303, M304. Drains of transistors M301, M302, M303 and M304 are tied to VDD through pull-up resistors R301, R302. Sources of the differential transistor pair M301, M302 are tied to a switch transistor M305, whose gate is driven by clock input clkn. Sources of cross-coupled transistor pair M303, M304 are tied to a drain of transistor switch M306, whose gate is driven by clock input clk. Current source transistor M307, whose gate is biased by voltage vb, supplies current to sources of switch transistors M305, M306. Latch 201 produces outputs (vop, von) as shown in FIG. 3.
FIG. 4 shows a circuit diagram of CML combination logic 102 of FIG. 1. As shown in FIG. 4, CML combination logic 102 includes four differential transistor pairs (M401, M402), (M403, M404), (M405, M406), (M407, M408), and (M409, M410) forming NAND and MUX gates. Switches M411, M412, and M413 are connected to sources of respective differential transistor pairs, as shown in FIG. 4. Tail current source transistors M414 and M415 supply current to the differential transistor pairs. Power supply voltage VDD is provided through pull-up resistors R401-R402, R403-R404, and outputs (vop, von) are connected to the pull-up resistors R403-R404 as shown in FIG. 4. The xe2x80x9cselxe2x80x9d signal is an internal signal of CML combination logic 102, and can be connected to power or ground. It sets the first output of (vop, von) to be logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d for duty cycle setting after reset and the xe2x80x9cselxe2x80x9d setting is up to the user. Note that it does not affect the reset operation.
FIG. 5 illustrates the circuit diagram of CML multiplexer 101. As shown in FIG. 5, CML multiplexer 101 includes two differential transistor pairs (M501, M502) and (M503, M504). Tail current source transistor M507 supplies current to sources of the differential transistor pairs (M501, M502) and (M503, M504) through switch transistors M505, M506. Switch transistors M505, M506 are driven by a reset and resetn (inverted reset) signal, respectively. Drains of differential transistor pairs (M501, M502), (M503, M504) are connected to the supply voltage VDD through pull-up resistors R501, R502, respectively, and to outputs (vop, von), respectively, as shown in FIG. 5.
To understand the reset operation of divide-by-N circuit, a reset of divide-by-2 is shown in FIG. 6 and is explained using the timing diagram of FIG. 7. First, the input (VSS, VDD) of multiplexer 101 is selected by reset. Second, the output (VSS, VDD) of multiplexer 101 is asserted at the input (vip, vin) of CML flip flop 103, and is read by the NMOS differential transistor pair M301, M302 of first CML latch 201A at a negative clock (clk) period (clk=LOW). Third, the output (VSS, VDD) of first CML latch 201A is held by NMOS cross-coupled transistor pair M303, M304 of first CML latch 201A of CML flip flop 103, and is read by the NMOS differential transistor pair M301, M302 of second CML latch 201B of CML flip flop 103 to the output (VSS, VDD) at the positive clk period (clk=HIGH). Fourth, the output (VSS, VDD) is held by NMOS cross-coupled transistor pair M303, M304 of second CML latch 201B at the negative elk period (clk=LOW). As a result, the output of CML flip flop 103 is reset to the initial state (VSS, VDD) at the second negative elk period (clk=LOW).
Since the conventional circuit resets (vip, vin), (qop, qon) and (vop, von) sequentially, its minimum reset duration must take slightly more than one clock period. For convenience, assume that one clock period is required for reset. Thus, the reset operation of a conventional divide-by-N is such that all the outputs of CML flip flops 103 are reset to the defined value (VSS, VDD) at one clock period.
The disadvantages of the conventional CML divide-by-N with asynchronous reset are as follows:
In a convention reset circuit, multiplexer 101 is used to define an initial state of the circuit. Multiplexer 101 introduces a delay when it is not being used (i.e. when no reset is applied to the circuit), however, the multiplexer is always in the signal path, introducing a delay. CML multiplexer 101 with a propagation delay (td) requires the minimum pulse width to be td+tsetup+thold. For example, td is 40 ns in the 1.2V 3.125 GHz Serdes standard, and it is 12.5% of full speed clock 3.125 GHz. As operational speed increases, the propagation delay td becomes a bottleneck.
Extra current consumption IMUX is needed for multiplexer 101 that provides the initial state. There is a dependence between the extra current consumption IMUX and the reset duration. If each CML flip flop 103 has its own multiplexer 101, then the current consumption is increased by Nxc3x97IMUX, but the reset duration stays at one clock period. Even if only the first CML flip flop 103 has its own multiplexer 101, the current consumption is slightly increased by IMUX, but the reset duration is increased to N clock periods.
The reset duration takes at least one clock period. For example, if clk is {fraction (1/20)} of full speed (system) clock, then the latency is a significant number of 20 UI (unit intervals).
Thus, conventional asynchronous reset circuits are unsuitable for low-power very-high-speed applications.
Accordingly, the present invention is directed to a circuit for asynchronous reset in current mode logic circuits that substantially obviates, one or more of the disadvantages of the related art.
There is provided a current mode logic (CML) flip flop including a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.
In another aspect there is provided a CML divide-by-N circuit including N CML flip flops connected in series, each flip flop inputting (vip, vin) signals and outputting (vop, von) signals. Each flip flop includes a first CML latch and a second CML latch. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch. A plurality of pull-up switches are driven by a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. Combination logic inputs the (vip, vin) signals and outputs the (vop, von) signals to set a duty cycle of the divide-by-N circuit.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.